Designs, develops, tests, and maintains physical IT hardware including servers, storage systems, and networking equipment
Terms (118)
- ๐ง Application-Specific Integrated Circuit
- ๐ง AutoAWQ
- โ๏ธ Automatic Mixed Precision
- & Binary AND
- ๐ก Binary Math
- โ Binary OR
- โ Binary XOR
- ๐งฎ Bitwise Operation
- ๐พ Block Storage
- ๐งฉ BoseโChaudhuriโHocquenghem Code
- ๐ฅ Burn-in
- ๐ฅ๏ธ CPU
- ๐ป Central Processing Unit (CPU)
- ๐ก Channel Coding
- ๐ก Coding Theory
- ๐ Common Logarithm
- ๐ ๏ธ Computer-Aided Design
- ๐งฎ Conjugate Gradient
- ๐๏ธ Control Theory
- โ๏ธ Data Parallelism
- ๐ง Deep Neural Network
- ๐งฟ Digital Twin
- ๐ฅ๏ธ Distributed Training
- ๐ง Dynamic Quantization
- ๐ฑ Edge AI
- ๐ Edge Deployment
- ๐ฒ Entropy Source
- ๐ก๏ธ Error-Correcting Code
- ๐ก Extended Kalman Filter
- ๐ข FP32
- ๐ง FPGA
- ๐ FasterTransformer
- ๐ง Field-Programmable Gate Array (FPGA)
- ๐๏ธ File System
- ๐ซ๏ธ Fog Computing
- ๐๏ธ GPU Inference
- ๐ GPU Utilization
- ๐งฎ Generator Matrix
- ๐งฎ Gradient Checkpointing
- ๐ฎ Graphics Processing Unit
- ๐ฎ Graphics Processing Unit Acceleration
- ๐พ HBM
- ๐๏ธ IEEE
- ๐งฎ IEEE 754
- โ๏ธ Instruction Set Architecture
- ๐ข Integer Arithmetic
- ๐ฅ๏ธ Intel
- ๐๏ธ International Electrotechnical Commission
- ๐ Keypoint Detection
- ๐ธ๏ธ LDPC Code
- ๐ง LLM Training
- โ๏ธ Loss Scaling
- ๐ MLPerf
- โ๏ธ Matrix Multiplication
- ๐งฑ Megatron-LM
- ๐ง Memory
- ๐ถ Memory Bandwidth
- ๐งฑ Memory Layout
- ๐ง Microarchitecture
- ๐ Microcontroller
- โ๏ธ Mixed Precision
- โ๏ธ Mixed Precision Training
- ๐ฑ MobileNet
- ๐ง Model Compression
- โ๏ธ Model Pruning
- โ Modular Arithmetic
- ๐ Modular Exponentiation
- ๐ง NPU
- ๐ฅ๏ธ NVIDIA
- โก NVIDIA H100
- ๐ Neural Processing Unit (NPU)
- ๐ถ Nyquist Frequency
- โ๏ธ OpenCL
- ๐๏ธ OpenCV
- ๐ค OpenVINO Toolkit
- โ๏ธ Parallel Computing
- โก Parallelism
- ๐งฎ Parity-Check Matrix
- ๐ฆ Payload Capacity
- ๐ง Permutation Box
- ๐ฒ Permuted Congruential Generator
- ๐ฆ Pipeline Parallelism
- ๐งฉ PyTorch Distributed
- โ๏ธ Quantum Computing
- ๐งช Quantum Error Correction
- โ๏ธ Qubits
- โ๏ธ ROCm
- ๐งช ReedโSolomon Code
- ๐ Ring-LWE
- ๐ฆ Router LM
- ๐ RunPod
- ๐ค SLAM
- ๐ SPHINCS+
- ๐ง SPICE
- ๐พ SSD
- ๐ Sampling Rate
- ๐ฐ๏ธ Sensor Fusion
- ๐๏ธ Stride
- ๐ Switch Transformer
- โ๏ธ TPU
- ๐งฐ TVM
- ๐ถ Temporal Key Integrity Protocol
- โ๏ธ Tensor Cores
- โ๏ธ Tensor Processing Unit (TPU)
- ๐ฑ TensorFlow Lite
- ๐ TensorRT
- โก TensorRT-LLM
- โ๏ธ The Enigma Machine
- ๐ Trusted Execution Environment
- ๐ก๏ธ Trusted Platform Module
- โป๏ธ Turbo Codes
- ๐ฟ Two Branches
- ๐ฎ VRAM
- ๐ถ๏ธ Virtual Reality
- ๐ถ Wavelet Transform
- ๐ข Weight Quantization
- ๐ XLA
- ๐ง ZeRO